1. Field of the Invention
The invention relates to a memory cell having multiple transistors and at least one storage capacitor, and in particular to a memory cell having three field-effect transistors (FET's).
2. Description of the Related Art
Memory units may include a charge storage unit, such as a capacitive component. Data may be represented as a charge or absence of charge in the charge storage unit. A leakage current may drain a charge stored in the charge storage unit. To compensate for leakage, the charge may be repeatedly and/or periodically refreshed. A refresh may include providing a current to the charge storage unit to build up the charge in the charge storage device. Memory units for which a clock signal for the refresh depends on a clock signal of a processor externally arranged from the memory unit may be referred to as dynamic random access memories (DRAM's). Where a clock signal for the refresh is generated by logic arranged on the same chip or with the memory may be referred to as an embedded DRAM or a pseudo-static read only memory (SRAM).
The memory unit may include a switch, such as a transistor, by which the charge storage device may be accessed. Data from a memory unit may be read by switching the transistor to determine whether charge is present in the charge storage device. Charge in the charge storage unit may also be drained during a read cycle.
Memory units having multiple transistors have been developed. However, such devices may not have a desirable reliability for reading data, or may take a larger area on a memory layout. Existing multi-transistor memory units may consume large amounts of power, take up large areas in a layout and have small fabrication yield. Existing three-transistor memory cells have capacitors with an electrode in the substrate and an electrode made of polycrystalline material. Other memory units include a complex stacked capacitor in a polycrystalline material directly above the substrate. Accordingly, the existing memory units having multiple transistors have a complex architecture that may be difficult to produce and have poor electrical properties.
Therefore, there is a need for a multi-transistor memory unit that may be constructed in a simple manner that is simple to produce with good electrical properties and a small layout area.